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fn8713 rev 6.00 page 1 of 23 september 22, 2016 fn8713 rev 6.00 september 22, 2016 isl78235 5a automotive synchronous buck regulator datasheet the isl78235 is a highly efficient, monolithic, synchronous step-down dc/dc converter that can deliver 5a of continuous output current from a 2.7v to 5.5v input supply. the device uses peak current mode control architecture to achieve very low duty cycle operation at high frequency with fast transient response and excellent loop stability. the isl78235 integrates a low on-resistance p-channel (35m , typical) high-side fet and n-channel (11m , typical) low-side fet to maximize efficiency and minimize external component count. the 100% duty cycle operation allows less than 250mv dropout voltage at 5a output current. the operating frequency of the pu lse width modulator (pwm) is adjustable from 500khz to 4mhz. the default switching frequency of 2mhz is set by connecting the fs pin high. the isl78235 can be configured for discontinuous (pfm) or forced continuous (pwm) oper ation at light load. forced continuous operation reduces no ise and rf interference, while discontinuous mode provides higher efficiency by reducing switching losses at light loads. fault protection is provided by internal hiccup mode current limiting during short-circuit and overcurrent conditions. the device also integrates output overvoltage and over-temperature protections. a power-good monitor indicates when the output is in regulation. the isl78235 offers a 1ms power-good (pg) timer at power-up. when in shutdown, the isl78235 discharges the output capacitor through an internal 100 soft-stop switch. other features include internal fixed or adjustable soft-start and internal/external compensation. the isl78235 is available in a 3mmx3mm 16 ld thin quad flat no-lead (tqfn) pb-free package and in a 5mmx5mm 16 ld wettable flank quad flat no-l ead (wfqfn) package with an exposed pad for improved thermal performance. the isl78235 is rated to operate across the temperature range of -40c to +105c in the 3mmx3mm package and -40c to +125c in the 5mmx5mm package. features ? 2.7v to 5.5v input voltage range ? 2mhz default switching frequency ? 100ns guaranteed phase minimum on time for wide output regulation ? adjustable switching freque ncy from 500khz to 4mhz ? external synchronization from 1mhz to 4mhz ? optional pfm mode for light-load efficiency improvement ? very low on-resistance hs/ls switches: 35m /11m ? internal 1ms or adjustable external soft-start ? soft-stop output discharge during disable ? otp, ocp, output ovp, input uvlo protections ? 1% reference accuracy over-temperature ?up to 95% efficiency ? aec-q100 qualified ? common pinout family allows migration from 3a to 5a without pcb change: - isl78233 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3a - isl78234 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4a - isl78235 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5a applications ? dc/dc pol modules ? c/p, fpga and dsp power ? video processor/soc power ? automotive infotainment power related literature ? ug015 , ?isl7823xeval1z evaluation board user guide? ? isl78233, isl78234 datasheet ? ug062 , ?isl7823xeval2z evaluation board user guide? figure 1. typical application: 5a buck regulator figure 2. efficiency vs load (v in = 5v; f sw = 2mhz; sync = gnd) 1 3 4 vin vdd sync vin phase phase comp 2 7 5 6 fb pgnd en fs pg ss 8 11 9 10 16 13 15 14 12 sgnd pgnd phase 2.7v to 5.5v v out 5a load dsp, fpga *isl78235 *pin compatible isl78233 - 3a buck isl78234 - 4a buck l c out c in 40 50 60 70 80 90 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 output load (a) efficiency (%) 4.5 5.0 2.5v out 1.2v out 3.3v out t a = +25c 100 1.5v out 1.8v out
isl78235 fn8713 rev 6.00 page 2 of 23 september 22, 2016 table of contents functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 typical operating performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 theory of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 pwm control scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 skip mode (pfm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 frequency adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 negative current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 pg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 uvlo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 soft start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 discharge mode (soft-stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 power mosfets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 100% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 output inductor and capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 loop compensation design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 pcb layout recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 l16.3x3d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 l16.5x5d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
isl78235 fn8713 rev 6.00 page 3 of 23 september 22, 2016 functional block diagram figure 3. functional block diagram phase + + csa + + ocp skip + + + slope comp slope soft start soft- eamp comp pwm/pfm logic controller protection hs driver fb + 0.85*vref pg sync shutdown vin pgnd oscillator zero-cross sensing bandgap scp + 0.5v en shutdown 1ms delay 55pf 100k sgnd 3pf 6k - - - - - - - vdd comp 100 shutdown ls driver fs iset threshold vref + neg current sensing p n + 0.8v - uv ov ss
isl78235 fn8713 rev 6.00 page 4 of 23 september 22, 2016 pin configuration isl78235 (16 ld tqfn, wfqfn) top view 1 3 4 vin vdd sync vin phase phase comp 2 7 5 6 fb pgnd en fs pg ss 8 11 9 10 16 13 15 14 12 sgnd pgnd phase epad pin descriptions pin number pin name description 1, 16 vin input supply voltage. place a minimum of two 22f low esr ceramic capacitors from vin to pgnd as close as possible to the ic for decoupling. 2 vdd input supply voltage for the logic circuitry. a 0.1f high frequency decoupling cera mic capacitor should also be placed close to the vdd and sgnd pin. connect to vin pin. 3 pg pg is an open-drain output for power-good indication. use a 10k to 100k pull-up resistor connected from pg to vin. at power-up or en high, pg rising edge is delayed by 1ms upon output voltage within regulation. 4 sync mode selection pin. connect to logic high or input voltage vin for forced pwm mode. connect to logic low or ground for pfm mode. connect to an external function generator for synchronization with a positive edge trigger. in external synchronization the isl78235 operat es in forced pwm mode. the transition to and from internal oscillator to external sy nchronization is seamless and does not require disabling of the isl78235. there is an internal 1m pull-down resistor to sgnd to prevent an undefined logic state if sync pin is floating. 5 en regulator enable pin. regulator is enabled when driven logic high. regulator is shutdown and phase pin discharge output capacitor when enable pin is driven low. 6 fs this pin sets the internal oscillator switching frequency using a resistor, r fs , from the fs pin to gnd. the frequency of operation may be programmed between 500khz to 4mhz. the switching frequency is 2mhz if fs is connected to vin. 7 ss ss is used to adjust the soft-start time. connect ss pin to sgnd for internal 1ms soft-start time. connect a capacitor from ss to sgnd to adjust the soft-start time. do not use more than 33nf on the ss pin. 8 comp comp is the output of the error amplifier if comp is not connected to vdd. an external compensation network must be used if comp is no t tied to vdd. if comp is tied to vdd, the error amplifier output is internally compensated. external compensation ne twork across comp and sgnd may be required to improve the loop compensa tion of the amplifier. 9 fb the feedback network of the regulator, fb, is the negative input to the transconductance error amplifier. the output voltage is set by an external resistor divider connected to fb. with a properly selected divider, the output voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.6v reference. in addition, the regulator power-good and un dervoltage protection circuitry use fb to monitor the regulator output voltage. 10 sgnd signal ground, connect to pgnd. 11, 12 pgnd power ground 13, 14, 15 phase switching node connections. connect to one te rminal of the inductor. this pin is discharged by a 100 resistor when the devi ce is disabled. see ? functional block diagram ? on page 3 for more detail. exposed pad epad the exposed pad must be connected to the sgnd pin for proper electrical performance. place as many vias as possible under the pad connecting to sg nd plane for optimal thermal performance.
isl78235 fn8713 rev 6.00 page 5 of 23 september 22, 2016 ordering information part number ( notes 1 , 2 , 3 ) part marking output voltage (v) temp. range (c) package (rohs compliant) pkg. dwg. # isl78235arz 8235 adjustable -40c to +105c 16 ld 3x3mm tqfn l16.3x3d ISL78235AARZ 78235a arz adjustable -40c to +125c 16 ld 5x5mm wfqfn l16.5x5d isl78235eval1z 3x3mm tqfn evaluation board isl78235eval2z 5x5mm wfqfn evaluation board notes: 1. add ?-t? suffix for 6k unit or ?-t7a? suffix for 250 unit tape and reel options. refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged pr oducts employ special pb-free material sets , molding compounds/die attach materials and 100% matte tin plate plus anneal (e3 termination finish, which is rohs complian t and compatible with both snpb and pb-free soldering operation s). intersil pb-free products are msl classified at pb-free peak reflow temperatures th at meet or exceed the pb-free requirements of ipc/jedec j std -020. 3. for moisture sensitivity level (msl), see the device information page for isl78235 . for more information on msl, see tech brief tb363 . table 1. key difference between family of parts part number i out max (a) isl78233 3 isl78234 4 isl78235 5
isl78235 fn8713 rev 6.00 page 6 of 23 september 22, 2016 typical application diagram figure 4. typical application diagram vin vdd pg sync pgnd fb pgnd sgnd 1 3 2 4 vout c 1 2x22 f c 3 * vin isl78235 2.7v to 5.5v +1.8v/5a r 1 100k powe r good indicator 100k r 3 r 2 200k l 1 2x22 f c 2 *c3 is optional. it is recommended to put a placeholder for it and check loop analysis before use. ceramic ceramic 0.68 h external synchronization input enable input r fs c ss r comp c comp vin phase phase phase comp ss fs fs en table 2. component selection table with internal compensation v out 1.2v 1.5v 1.8v 2.5v 3.3v c 1 2 x 22f 2 x 22f 2 x 22f 2x22f 2 x 22f c 2 ( note 4 ) 3 x 22f 3 x 22f 2 x 22f 2 x 22f 2 x 22f c 3 22pf 10pf 10pf 10pf 10pf l 1 0.33h-0.68h 0.33h-0.68h 0.33h-0.68h 0.47h-0.78h 0.47h-0.78h r 2 100k 150k 200k 316k 450k r 3 100k 100k 100k 100k 100k note: 4. c 2 values are minimum recommended values for ceramic capacitors. hi gher capacitance may be needed based on system requirements.
isl78235 fn8713 rev 6.00 page 7 of 23 september 22, 2016 absolute maximum ratings (reference to gnd) thermal information vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 5.8v (dc) or 7v (20ms) en, fs, pg, sync, vfb . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vin + 0.3v phase . . . . . . . . . . . . -1.5v (100ns)/-0.3v (dc) to 6.5v (dc) or 7v (20ms) comp, ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.7v esd rating human body model (tested per aec-q100-002) . . . . . . . . . . . . . . . . 5kv machine model (tested per aec-q100-003) . . . . . . . . . . . . . . . . . . 300v charge device model (tested per aec-q100-011) . . . . . . . . . . . . . . . 2kv latch-up (tested per aec-q100-004, class ii, level a) . . . . . . . . . . 100ma thermal resistance ? ja (c/w) ? jc (c/w) 16 ld tqfn package ( notes 5 , 6 ) . . . . . . . 43 3.5 16 ld wfqfn package ( notes 5 , 6 ) . . . . . 33 3.5 operating junction temperature range . . . . . . . . . . . . . .-55c to +125c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions vin supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v load current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0a to 5a ambient temperature range 3x3mm tqfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +105c 5x5mm wfqfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 6. ? jc , ?case temperature? location is at the center of the exposed metal pad on the package underside. electrical specifications specification limits are established at the following conditions: t a = -40c to +105c or t a = -40c to +125c depending on package, v in = 3.6v, en = v in , unless otherwise noted. typical values are at t a = +25c. boldface limits apply across the operating temperature range specified in the recommended oper ating conditions table for the specified package. parameter symbol test conditions min ( note 7 )typ max ( note 7 )unit input supply vin undervoltage lockout threshold v uvlo rising, no load 2.5 2.7 v falling, no load 2.20 2.45 v quiescent supply current i vin sync = gnd, no load at the output 47 a sync = gnd, no load at the output and no switches switching 47 60 a sync = v in , f sw = 2mhz, no load at the output 19 25 ma shutdown supply current i sd sync = gnd, v in = 5.5v, en = low 4 10 a output regulation reference voltage v ref 0.594 0.600 0.606 v vfb bias current i vfb vfb = 0.75v 0.1 a line regulation v in = v o + 0.5v to 5.5v (minimal 2.7v) 0.2 %/v soft-start ramp time cycle ss = sgnd 1 ms soft-start charging current i ss v ss = 0.1v 1.7 2.1 2.5 a overcurrent protection current limit blanking time t ocon 17 clock pulses overcurrent and auto restart period t ocoff 8 ss cycle positive peak current limit i plimit t a = +25c 6.2 7.8 9.4 a t a = -40c to +105c 6.1 11.0 a 5x5 mm wfqfn package t a = +105c to +125c 12.5 a peak skip limit i skip t a = +25c 0.85 1.10 1.40 a t a = -40c to +105c 0.83 1.60 a 5x5 mm wfqfn package t a = +105c to +125c 1.65 a
isl78235 fn8713 rev 6.00 page 8 of 23 september 22, 2016 zero cross threshold -275 375 ma negative current limit i nlimit t a = +25c -5.1 -2.8 -1.3 a -6.0 -0.6 a compensation error amplifier transconductance comp = vdd, internal compensation 125 a/v external compensation 130 a/v transresistance rt t a = -40c to +105c 0.11 0.17 0.22 5x5 mm wfqfn package t a = +105c to +125c 0.1 mosfet p-channel on-resistance v in = 5v, i o = 200ma 26 35 50 m v in = 2.7v, i o = 200ma 38 52 78 m n-channel on-resistance v in = 5v, i o = 200ma 5 11 20 m v in = 2.7v, i o = 200ma 8 15 31 m phase phase maximum duty cycle 100 % phase minimum on-time sync = high 100 ns oscillator nominal switching frequency f sw fs = v in 1730 2000 2350 khz fs with rs = 402k 420 khz fs with rs = 42.2k 4200 khz sync logic low to high threshold 0.67 0.75 0.84 v sync logic hysteresis 0.10 0.17 0.20 v sync logic input leakage current sync = 3.6v 3.7 5.0 a power-good (pg) output low voltage i pg = 1ma 0.3 v pg delay time (rising edge) time from v out reached regulation 0.5 1.0 2.0 ms pg delay time (falling edge) 6.5 s pg pin leakage current pg = v in 0.01 0.10 a ovp pg rising threshold 0.80 v uvp pg rising threshold 80 85 90 % uvp pg hysteresis 5.5 % en logic input low 0.4 v logic input high 0.9 v en logic input leakage current en = 3.6v 0.1 1.0 a over-temperature protection thermal shutdown temperature rising 150 c thermal shutdown hysteresis temperature falling 25 c note: 7. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. electrical specifications specification limits are established at the following conditions: t a = -40c to +105c or t a = -40c to +125c depending on package, v in = 3.6v, en = v in , unless otherwise noted. typical values are at t a = +25c. boldface limits apply across the operating temperature range specified in the recommended oper ating conditions table for the specified package. (continued) parameter symbol test conditions min ( note 7 )typ max ( note 7 )unit
isl78235 fn8713 rev 6.00 page 9 of 23 september 22, 2016 typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v in =v dd = 5v, v out =1.8v, en=v dd , sync = v dd , l = 0.68h, f sw = 2mhz, c in = 2 x 22f, c out = 2 x 22f, i out = 0a to 5a. figure 5. efficiency vs load (3.3v in ; sync = vdd) figure 6. efficiency vs load (3.3v in ; sync = gnd) figure 7. efficiency vs load ( 5v in ; sync = vdd ) figure 8. efficiency vs load ( 5v in ; sync = gnd) figure 9. power dissipation vs load ( 3.3v in ; sync = vdd ) figure 10. power dissipation vs load ( 5v in ; sync = vdd ) 40 50 60 70 80 90 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 output load (a) efficiency (%) 4.5 5.0 1.2v out 2.5v out 1.8v out 1.5v out 1.0v out 40 50 60 70 80 90 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output load (a) efficiency (%) 0.9v out 1.2v out 1.5v out 1.8v out 2.5v out 40 50 60 70 80 90 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 output load (a) efficiency (%) 4.5 5.0 1.2v out 1.5v out 3.3v out 2.5v out 1.8v out 40 50 60 70 80 90 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 output load (a) efficiency (%) 4.5 5.0 3.3v out 1.2v out 1.5v out 1.8v out 2.5v out 0 0.5 1.0 1.5 2.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 output load (a) power dissipation (w) 4.5 5.0 2.5 1.8v out 2.5v out 1.0v out 1.2v out 0 0.5 1.0 1.5 2.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 output load (a) power dissipation (w) 4.5 5.0 2.5 1.2v out 1.8v out 2.5v out 3.3v out
isl78235 fn8713 rev 6.00 page 10 of 23 september 22, 2016 figure 11. v out regulation vs load (v out = 1.2v) figure 12. v out regulation vs load (v out = 1.8v) figure 13. v out regulation vs load (v out =1.0v) figure 14. phase minimum on-time vs v in figure 15. en start-up at no load (sync = gnd) figure 16. en start-up at no load (sync = vdd) typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v in =v dd = 5v, v out =1.8v, en=v dd , sync = v dd , l = 0.68h, f sw = 2mhz, c in = 2 x 22f, c out = 2 x 22f, i out = 0a to 5a. (continued) 1.179 1.184 1.194 1.199 1.204 1.209 1.214 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 output load (a) output voltage (v) 4.5 5.0 1.219 1.189 3.3v pwm 5v pfm 5v pwm 3.3v pfm 1.770 1.775 1.785 1.790 1.795 1.800 1.805 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 output load (a) 4.5 5.0 1.810 1.780 output voltage (v) 5v pwm 3.3v pwm 5v pfm 3.3v pfm 0.980 0.985 0.995 1.000 1.005 1.010 1.015 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 output load (a) output voltage (v) 4.5 5.0 1.020 0.990 3.3v pfm 3.3v pwm 50 55 60 65 70 75 3.0 3.5 4.0 4.5 5.0 5.5 v in (v) phase minimum on-time (ns) t = +25c t = -40c t = +125c phase 5v/div en 2v/div pg 5v/div v out 1v/div 500s/div ss = gnd c out = 4 x 22f phase 5v/div en 2v/div pg 5v/div v out 1v/div 500s/div ss = gnd c out = 4 x 22f
isl78235 fn8713 rev 6.00 page 11 of 23 september 22, 2016 figure 17. v in start-up at no load (sync = gnd) figure 18. v in start-up at no load (sync = vdd) figure 19. en shutdown at no load (sync = gnd) figure 20. en shutdown at no load (sync = vdd) figure 21. v in shutdown at no load (sync = gnd) figure 22. v in shutdown at no load (sync = vdd) typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v in =v dd = 5v, v out =1.8v, en=v dd , sync = v dd , l = 0.68h, f sw = 2mhz, c in = 2 x 22f, c out = 2 x 22f, i out = 0a to 5a. (continued) phase 5v/div v in 2v/div pg 5v/div v out 1v/div 500s/div ss = gnd c out = 4 x 22f phase 5v/div v in 2v/div pg 5v/div v out 1v/div 500s/div ss = gnd c out = 4 x 22f phase 5v/div en 2v/div pg 5v/div v out 1v/div 1ms/div ss = gnd c out = 4 x 22f phase 5v/div en 2v/div pg 5v/div v out 1v/div 1ms/div ss = gnd c out = 4 x 22f phase 5v/div v in 2v/div pg 2v/div v out 1v/div 2ms/div ss = gnd c out = 4 x 22f phase 5v/div v in 2v/div pg 2v/div v out 1v/div 2ms/div ss = gnd c out = 4 x 22f
isl78235 fn8713 rev 6.00 page 12 of 23 september 22, 2016 figure 23. en start-up at 5a load (sync = gnd) figure 24. en start-up at 5a load (sync = vdd) figure 25. v in start-up at 5a load (sync = gnd) figure 26. v in start-up at 5a load (sync = vdd) figure 27. en shut-down at 5a load (sync = gnd) figure 28. en shut-down at 5a load (sync = vdd) typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v in =v dd = 5v, v out =1.8v, en=v dd , sync = v dd , l = 0.68h, f sw = 2mhz, c in = 2 x 22f, c out = 2 x 22f, i out = 0a to 5a. (continued) i out 5a/div en 2v/div pg 5v/div v out 1v/div 500s/div ss = gnd c out = 4 x 22f i out 5a/div en 2v/div pg 5v/div v out 1v/div 500s/div ss = gnd c out = 4 x 22f i out 5a/div v in 5v/div pg 5v/div v out 1v/div 500s/div ss = gnd c out = 4 x 22f i out 5a/div v in 5v/div pg 5v/div v out 1v/div 500s/div ss = gnd c out = 4 x 22f i out 5a/div en 2v/div pg 5v/div v out 1v/div 100s/div ss = gnd c out = 4 x 22f i out 5a/div en 2v/div pg 5v/div v out 1v/div 100s/div ss = gnd c out = 4 x 22f
isl78235 fn8713 rev 6.00 page 13 of 23 september 22, 2016 figure 29. jitter at no load (sync = vdd) figure 30. jitter at 5a load (sync = vdd) figure 31. steady state at no load (sync = gnd) figure 32. steady state at no load (sync = vdd) figure 33. steady state at 5a (sync = vdd) typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v in =v dd = 5v, v out =1.8v, en=v dd , sync = v dd , l = 0.68h, f sw = 2mhz, c in = 2 x 22f, c out = 2 x 22f, i out = 0a to 5a. (continued) 5ns/div phase 1v/div 5ns/div phase 1v/div phase 5v/div i_phase 1a/div ac v out 20mv/div ac 20ms/div c out = 4 x 22f phase 5v/div i_phase 1a/div ac v out 20mv/div ac 200ns/div c out = 4 x 22f phase 5v/div i_phase 1a/div ac v out 20mv/div ac 200ns/div c out = 4 x 22f
isl78235 fn8713 rev 6.00 page 14 of 23 september 22, 2016 figure 34. load transient 0a to 5a; 0.5a/s (sync = gnd) figure 35. load transient 0a to 5a; 0.5a/s (sync = vdd) figure 36. output short-circuit figure 37. output short-circuit recovery to 1a load figure 38. short-circuit hiccup waveform figure 39. overcurrent protection typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v in =v dd = 5v, v out =1.8v, en=v dd , sync = v dd , l = 0.68h, f sw = 2mhz, c in = 2 x 22f, c out = 2 x 22f, i out = 0a to 5a. (continued) i_load 2a/div v out 100mv/div ac 500s/div r comp = 154k c comp = 220pf c out = 4 x 22f 500s/div r comp = 154k c comp = 220pf i_load 2a/div v out 100mv/div ac c out = 4 x 22f v out phase i_phase pg v out phase i_phase pg v out ss i_phase i_load c ss = 33nf v out phase i_phase pg load = 4a to 8a step
isl78235 fn8713 rev 6.00 page 15 of 23 september 22, 2016 figure 40. overvoltage protection figure 41. overvoltage recovery figure 42. over-temperature protection figure 43. over-temperature recovery typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v in =v dd = 5v, v out =1.8v, en=v dd , sync = v dd , l = 0.68h, f sw = 2mhz, c in = 2 x 22f, c out = 2 x 22f, i out = 0a to 5a. (continued) v out phase i_phase pg v out into 3v supply v out phase i_phase pg v out from 3v supply v out pg v_temp +125c to +170c transient load = 4a temp = (v_temp-1.1092)/4.1mv v out pg v_temp +125c to +170c transient load = 4a temp = (v_temp-1.1092)/4.1mv
isl78235 fn8713 rev 6.00 page 16 of 23 september 22, 2016 theory of operation the isl78235 is a step-down switching regulator optimized for automotive point-of-load powered applications. the regulator operates at a 2mhz default switching frequency for high efficiency and smaller form factor while staying out of the am frequency band. by connecting a resistor from fs to sgnd, the operational frequency is adjustable in the range of 500khz to 4mhz. at light load, the regulator reduces the switching frequency by operating in pulse frequency modulation (pfm) mode, unless forced to operate in fixed frequency pwm mode, to minimize the switching loss and to maximize the battery life. the quiescent current when the output is not loaded is typically only 45a. the supply current is typically only 3.8a when the regulator is shut down. pwm control scheme pulling the sync pin hi (>0.8v) forces the converter into pwm mode, regardless of output curre nt, bypassing the pfm operation at light load. the isl78235 em ploys the current-mode pulse width modulation (pwm) control scheme for fast transient response and pulse-by-pulse current limiting (see figure 3 on page 3 ). the current loop consists of the oscillator, the pwm comparator, current-sensing circuit and the slope compensation for the current loop stability. the slope compensation is 440mv/ts (ts is the switching period), which changes proportionally with frequency. the gain for the current-sensing circuit is ty pically 170mv/a. the control reference for the current loops comes from the error amplifier's (eamp) output. the pwm operation is initialized by the clock from the oscillator. the p-channel mosfet is turned on at the beginning of a pwm cycle and the current in the mosfet starts to ramp up. when the sum of the current amplifier csa and the slope compensation reaches the control reference of the current loop, the pwm comparator comp sends a signal to the pwm logic to turn off the pfet and turn on the n-channel mosfet. the nfet stays on until the end of the pwm cycle. figure 44 shows the typical operating waveforms during the pwm operation. the dotted lines on v csa illustrate the sum of the slope compensation ramp and the current-sense amplifier?s csa output. the output voltage is regulated by controlling the v eamp voltage to the current loop. the bandgap circuit outputs a 0.6v reference voltage to the voltage loop. the feedback signal comes from the vfb pin. the soft-start block only affects the operation during the start-up and is discussed separately. the error amplifier is a transconductance amplifier that co nverts the voltage error signal to a current output. the voltage loop is internally compensated with the 55pf and 100k rc network. the maximum eamp voltage output is precisely clamped to 2.5v. skip mode (pfm) pulling the sync pin low (<0.4v), forces the converter into pfm mode. the isl78235 enters a pulse-skipping mode at light load to minimize the switching loss by reducing the switching frequency. figure 45 on page 17 illustrates the skip mode operation. a zero-cross sensing circuit shown in figure 3 on page 3 monitors the nfet current for zero crossing. when 16 consecutive cycles are detected, the regulator enters the skip mode. during the sixteen detecting cycles, the current in the inductor is allowed to become negative. the counter is reset to zero when the current in any cycle does not cross zero. once the skip mode is entered, the pulse modulation starts being controlled by the skip comparator shown in figure 3 on page 3 . each pulse cycle is still synchronized by the pwm clock. the pfet is turned on at the clock's rising edge and turned off when the output is higher than 1.2% of the nominal regulation or when its current reaches the peak skip current limit value. then, the inductor current is discharging to 0a and stays at zero (the internal clock is disabled), and the output voltage reduces gradually due to the load current discharging the output capacitor. when the output voltage drops to the nominal voltage, the pfet will be turned on again at the rising edge of the internal clock as it repeats the previous operations. the regulator resumes normal pwm mode operation when the output voltage drops 1.2% below the nominal voltage. figure 44. pwm operation waveforms v eamp v csa duty cycle i l v out
isl78235 fn8713 rev 6.00 page 17 of 23 september 22, 2016 frequency adjust the frequency of operation is fixed at 2mhz when fs is tied to vin. the switching frequency is adjustable in the range from 500khz to 4mhz with a resistor from fs to sgnd according to equation 1 : the isl78235 also has frequency synchronization capability by connecting the sync pin to an external square pulse waveform. the frequency synchronization feature will synchronize the positive edge trigger and its swit ching frequency up to 4mhz. the synchronization positive pulse width should be 100ns or greater for proper operation. the minimum external sync frequency is half of the free running oscillator frequency (either the default 2mhz when fs tied to vin or determined by the resistor from fs to sgnd). overcurrent protection the overcurrent protection is realized by monitoring the csa output with the ocp comparator, as shown in figure 3 on page 3 . the current-sensing circuit has a gain of 170mv/a typical, from the pfet current to the csa outp ut. when the csa output reaches the threshold, the ocp comparator is tripped to turn off the pfet immediately. the overcurrent fu nction protects the switching converter from a shorted output by monitoring the current flowing through the upper mosfet. upon detection of an overcurrent condition, the upper mosfet is immediately turned off and is not turned on again until the next switching cycle. upon detection of the initial overcurrent condition, the overcurrent fault counter is set to 1. if on the subsequent cycle another overcurrent condition is detected, the oc fault counter is incremented. if there are 17 sequential oc fault detections, the regulator is shut down under an overcurrent fault condition. an overcurrent fault condition results in the regulator attempting to restart in a hiccup mode within the delay of eight soft-start periods. at the end of the 8th soft-start wait period, the fault counters are re set and soft-start is attempted again. if the overcurrent condition goes away during the delay of 8 soft-start periods, the output w ill resume back into regulation point after hiccup mode expires. negative current protection similar to overcurrent, the negative current protection is realized by monitoring the current across the low-side nfet, as shown in figure 3 on page 3 . when the valley point of the inductor current reaches -3a for 4 consecutive cycles , both pfet and nfet are off. a 100 discharge circuit in parallel to the nfet activates to discharge the output into regu lation. the regulator resumes switching operation when output is within regulation. the regulator will be in pfm for 20s before switching to pwm if necessary. pg pg is an open-drain output of a window comparator that continuously monitors the buck re gulator output voltage. pg is actively held low when en is low and during the buck regulator soft-start period. a 1ms delay after the soft-start period, pg becomes high impedance as long as the output voltage is within nominal regulation voltage set by vfb. when the voltage at fb pin drops 15% below 0.6v or rises above 0.8v, the isl78235 pulls pg low. any fault condition forces pg low until the fault condition is cleared and after soft-start completes. for logic level output voltages, connect an external pull-u p resistor between pg and vin. a 100k resistor works well in most applications. uvlo when the input voltage is below the undervoltage lockout (uvlo) threshold (2.5v typical), the regulator is disabled. soft start-up the soft start-up circuit redu ces the inrush current during power- up. the soft-start block outputs a ramp reference to the input of the error amplifier. this voltage ramp limits the slew rate of inductor current as well as the output voltage, so that the output voltage rises in a controlled fashion. when vfb is less than 0.1v at the beginning of the soft-start, the switching frequency is reduced to 200khz, so that the output can start-up smoothly at light load condition. during soft-start, the ic operates in the skip mode to support prebiased output condition. figure 45. skip mode operation waveforms clock i l v out nominal +1.2% nominal pfm current limit 0 16 cycles pwm pfm nominal -1.2% pwm load current r fs k ? ?? 220 10 3 ? f osc khz ?? ------------------------------ 14 C = (eq. 1)
isl78235 fn8713 rev 6.00 page 18 of 23 september 22, 2016 tie ss to sgnd for internal soft-start (1ms typical). connect a capacitor from ss to sgnd to adjust the soft-start time. this capacitor, along with an internal 2.1a current source, sets the soft-start interval of the converter, t ss as shown by equation 2 . c ss must be less than 33nf to insure proper soft-start reset after fault condition. enable the enable (en) input allows the us er to control the turning on or off of the regulator for purposes such as power-up sequencing or minimizing power dissipation wh en the output is not needed. when the regulator is enabled, there is typically a 600s delay for waking up the bandgap reference and then the soft start-up begins. discharge mode (soft-stop) when a transition to shutdown mode occurs, (en low or fault condition) or the v in uvlo is set, the output is discharged to gnd through an internal 100 switch on the phase pin. power mosfets the power mosfets are optimized for highest efficiency. the on-resistance for the pfet is typically 35m and the on-resistance for the nfet is typically 11m . 100% duty cycle the isl78235 features a 100% duty cycle operation to maximize the battery operation life and provide very low dropout down to the minimum operating voltage. when the battery voltage drops to a level that the isl78235 can no longer maintain the regulation at the output, the regulator completely turns on the pfet. the maximum dropout voltage under the 100% duty cycle operation is the product of the load current and the on-resistance of the pfet. thermal shutdown the isl78235 has built-in over-temperature thermal protection. when the internal temperature reaches +150c, the regulator completely shuts down. as the temperature drops to +125c, the isl78235 resumes operation after a soft-start cycle. applications information output inductor and capacitor selection to consider steady state and transient operation, the isl78235 typically uses a 0.33h to 0.78h output inductor. higher or lower inductor values can be used to optimize the total converter system performance. for example, for a higher output voltage 3.3v application, in order to decrease the inductor current ripple and output voltage ripple, the output inductor value can be increased. it is recommended to set the ripple inductor current to approximately 30% of the maximu m output current for optimized performance. the inductor ripple current can be expressed as shown in equation 3 : the inductor?s saturation current rating needs to be larger than the positive peak current limi t specified in the electrical specification table. the isl78235 has a typical peak current limit of 7.5a. the inductor saturation current needs to be over 7.5a for proper operation. the isl78235 uses an internal compensation network for regulator stability and the output capacitor value is dependent on the output voltage. the recommended ceramic capacitors are low esr x7r rated or better. the recommended minimum output capacitor values are shown in table 2 on page 6 . table 2 , shows the minimum output capacitor value is given for the different output voltages to make sure that the whole converter system is stable. additional output capacitance should be added for better performance in applications where high load transient or low output ripple is required. it is recommended to check the system level performance along with the simulation model. output voltage selection the output voltage of the regulator is programmed with an external resistor divider that is used to scale the output voltage relative to the internal reference voltage (0.6v) and fed back to the inverting input of the error amplifier fb pin (see figure 46 ). the output voltage programming resistor r 2 (from vout to fb) will depend on the value chosen for the feedback resistor and the desired output voltage of the regulator. the value for the feedback resistor, r 3 (from fb to gnd), is typically between 10k and 100k . r 2 is chosen as shown in equation 4 . where vfb = 0.6v and v out is the output voltage. c ss ? f ?? 3.1 t ss s ?? ? = (eq. 2) ? i v out 1 v out v in --------------- - C ?? ?? ?? ? lf sw ? ---------------------------------------------------- - = (eq. 3) figure 46. programming output voltage with r 2 and r 3 1 3 4 vin vdd sync vin phase phase comp 2 7 5 6 fb pgnd en fs pg ss 8 11 9 10 16 13 15 14 12 sgnd pgnd phase v out isl78235 r 2 v in r 3 r 2 r 3 v out vfb --------------- - 1 C ?? ?? = (eq. 4)
isl78235 fn8713 rev 6.00 page 19 of 23 september 22, 2016 there is a leakage current from vin to phase. it is recommended to preload the output with 10a minimum for accurate output voltage. for improved loop stability performance, add 10pf to 22pf in parallel with r 2 . check loop analysis before use in application. see ? loop compensation design ? for more information. input capacitor selection the main functions for the input capacitor are to provide decoupling of the parasitic inductance and to provide a filtering function to prevent the switching current flowing back to the input rail. two 22f low esr x7r rated ceramic capacitors in parallel with a 0.1f high frequency decoupling capacitor placed very close to the vin/vdd and sgnd/pgnd pins is a good starting point for the input capacitor selection. loop compensation design when comp is not connected to vdd, the comp pin is active for external loop compensation. the isl78235 uses constant frequency peak current mode control architecture to achieve a fast loop transient response. an accurate current-sensing circuit in parallel with the upper mosfet is used for peak current control signal and overcurrent protection. the inductor is not considered as a state variable si nce its peak current is constant and the system becomes a single or der system. it is much easier to design a type ii compensator to stabilize the loop than to implement voltage mode control. peak current mode control has an inherent input voltage feed-forward function to achieve good line regulation. figure 47 shows the small signal model of the synchronous buck regulator. figure 48 shows the type ii compensator and its transfer function is expressed as equation 5 : where, compensator design goal: high dc gain choose loop bandwidth f c ~100khz or less gain margin: >10db phase margin: >40 the compensator design procedure is as follows: the loop gain at crossover frequency of f c has a unity gain. therefore, the compensator resistance r 6 is determined by equation 6 . where gm is the transconductance, g m , of the voltage error amplifier and r t is the gain of the current sense amplifier. compensator capacitors c 6 and c 7 are given by equation 7 . put one compensator pole at zero frequency to achieve high dc gain, and put another compensator pole at either esr zero frequency or half switching frequency, whichever is lower in equation 7 . an optional zero can boost the phase margin. ? cz2 is a zero due to r 2 and c 3 ? put compensator zero 2 to 5 times f c : d v in d i l in in i l + 1:d + l i co rc -av(s) d comp v r t fm he(s) + t i (s) k o v t v (s) i l p + 1:d + rc ro -av(s) r t fm he(s) t i (s) k o t(s) ^ ^ v ^ ^ ^ ^ ^ ^ figure 47. small signal model of synchronous buck regulator r lp gain (v loop (s(fi)) - + r 6 v ref v fb vo gm v comp c 7 - + c 6 ref fb vo figure 48. type ii compensator c 3 r 2 r 3 a v s ?? v ? comp v ? fb ---------------- - gm r 3 ? c 6 c 7 + ?? r 2 r 3 + ?? ? -------------------------------------------------------- 1 s ? cz1 ------------ - + ?? ?? 1 s ? cz2 ------------ - + ?? ?? s1 s ? cp1 ------------- + ?? ?? 1 s ? cp2 ------------- + ?? ?? -------------------------------------------------------------- - = = (eq. 5) ? cz1 1 r 6 c 6 -------------- - ? cz2 1 r 2 c 3 -------------- - = ? cp1 ? c 6 c 7 + r 6 c 6 c 7 ---------------------- - ? cp2 r 2 r 3 + c 3 r 2 r 3 ---------------------- - = ? = , = r 6 2 ? f c v o c o r t gm v fb ? --------------------------------- - 13.7 3 ? 10 f c v o c o ? == (eq. 6) c 6 r o c o r 6 -------------- - v o c o i o r 6 -------------- - c 7 max r c c o r 6 -------------- - 1 ? f s r 6 --------------- - (, ) = , = = (eq. 7) c 3 1 ? f c r 2 --------------- - = (eq. 8)
isl78235 fn8713 rev 6.00 page 20 of 23 september 22, 2016 example: v in = 5v, v o = 1.8v, i o = 5a, f sw = 2mhz, r 2 = 200k , r 3 = 100k , c o = 2 x22f/10m , l = 0.68h, f c = 100khz, then compensator resistance r 6 : it is acceptable to use 107k ? as the ? closest standard value for r 6 . it is also acceptable to use th e closest standard values for c 6 and c 7 . there is approximately 3pf parasitic capacitance from v comp to gnd. therefore, c 7 is optional. use c 6 = 150pf and c 7 = open. use c 3 = 10pf. note that c 3 may increase the loop bandwidth from previous estimated value. figure 49 shows the simulated voltage loop gain. it is show n that it has a 120khz loop bandwidth with a 58 phase margin and 8db gain margin. it may be more desirable to achieve an increased phase and gain margin. this can be accomplished by lowering r 6 by 10% to 20%. pcb layout recommendation the pcb layout is a very important converter design step to make sure the designed converter wo rks well. for the isl78235 the power loop is composed of the output inductor l 0 , the output capacitor c o , the phase pins and the pgnd pin. it is necessary to make the power loop as small as possible and the connecting traces among them should be direct, short and wide. the switching node of the converter, the phase pins and the traces connected to the node are very noisy, so keep the voltage feedback trace away from these noisy traces. the input capacitor should be placed as close as po ssible to the vin pin. the ground of the input and output capacitors should be connected as close as possible. the heat of the ic is mainly dissipated through the thermal pad. maximizing the copper area connected to the thermal pad is preferable. in addition, a solid ground plane is helpful for better emi performance. refer to tb389 for via placement on the copper area of the pcb underneath the thermal pad for optimum thermal performance. r 6 13.7 3 ? 10 100khz 1.8v 44 ? f ? ? ? 108k ? == (eq. 9) c 6 1.8v 44 ?? f 5a 107k ? ? ------------------------------- - 148pf = = (eq. 10) c 7 max 10m ? 44 ? f ? 107k ? ----------------------------------- - 1 ? 2mhz 107k ? ?? ? ------------------------------------------------ (, ) 4.1pf 1.5pf (,) = = (eq. 11) c 3 1 ? 100khz 200k ? ? ------------------------------------------------ = 16pf = (eq. 12) figure 49. simulated loop gain and phase 60 40 20 0 -20 -40 -60 100 1k 10k 100k 1m frequency (hz) 150 100 50 0 -50 -100 -150 100 1k 10k 100k 1m frequency (hz) closed loop phae () closed loop gain (db) 200
fn8713 rev 6.00 page 21 of 23 september 22, 2016 isl78235 intersil automotive qualified products are manufactured, asse mbled and tested utilizing ts16949 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2015-2016. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support . revision history the revision history provided is for in formational purposes only and is believ ed to be accurate, but not warranted. please visit our website to make sure you have the latest revision. date revision change september 22, 2016 fn8713.6 corrected shifted connection in block diagram on page 3. april 1, 2016 fn8713.5 updated figure 10 title on page 9. december 11, 2015 fn8713.4 added a new user guide to related literature section on page 1. added isl78235eval2z to the ordering information table on page 5. added table1 on page 5. november 10, 2015 fn8713.3 added 5x5mmwfqfn information throughout datasheet. removed ?li-ion battery powered devices? application bullet from page 1. updated note 1 on page 5 from ?add ?-t*? suffix for tape and reel.? to ?add ?-t? suffix for 6k unit or ?-t7a? suffix for 250 unit tape and reel options.? on page 8, removed the test condition ?t a = -40c to +105c? for the i nlimit specifications. on page 8, added ?t a = -40c to +105c to the test conditions of the transresistance specification.? in ?pwm control scheme? on page 16 (last sentence ) corrected a typo by changing ?1.6v to ?2.5v?. updated the ?pcb layout recommendation? section. july 1, 2015 fn8713.2 figures 15 through 28 changed ?css = 33nf? to ?ss = gnd?. february 20, 2015 fn8713.1 electrical sp ec table, oscillator section on page 8: changed nominal switching frequency minimum from 1700khz to 1730khz. february 3, 2015 fn8713.0 initial release
isl78235 fn8713 rev 6.00 page 22 of 23 september 22, 2016 package outline drawing l16.3x3d 16 lead thin quad flat no-lead plastic package rev 0, 3/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance: decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.25mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view (4x) 0.15 index area pin 1 a 3.00 b 3.00 pin #1 b 0.10 m a c 4 6 6 0.05 1 12 4 9 13 16 8 5 1.60 sq 16x 0.23 16x 0.400.10 4x 1.50 12x 0.50 (16x 0.60) ( 1.60) (2.80 typ) (16x 0.23) (12x 0.50) c 0 . 2 ref 0 . 05 max. 0 . 02 nom. 5 0.75 0.05 0.08 0.10 c c c index area see detail x jedec reference drawing: mo-220 weed. 7. for the most recent package outline drawing, see l16.3x3d .
isl78235 fn8713 rev 6.00 page 23 of 23 september 22, 2016 package outline drawing l16.5x5d 16 lead quad flat no-lead plastic package (punch qfn with wettable flank) rev 2, 5/14 located within the zone indicat ed. the pin #1 identifier may be unless otherwise specified, tolerance: decimal 0.05 the configuration of the pin #1 identifier is opt ional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the plat ed terminal and is measured dimensions in ( ) are for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 5. either a mold or mark feature. 3. 4. 2. dimensions are in millimeters. 1. notes: top view bottom view typical recommended land pattern side view 5.00 4.75 0.10 c a (2x) 5.00 4.75 a 5 0.50 dia 3 2 1 16 12x (0.80) 16x (0.30) (4.80) sq (2.80) sq reference document: jedec m0220. 6. (0.01) section c-c scale: none detail a (dimple depth) scale: none 0.20 0.10 4 4 0.10 c b (2x) 0.10 c b (2x) 0.10 c a (2x) b 0.60 max. (4x) 0.60 max. (4x) 2.8 pin 1 id r0.20 0.45 16 2.8 (0.70) 0.150.10 (0.70) 0.400.10 terminal tip 4 0.10 m c a b 0.10 m c a b 0.10 0.05 m m cab c 0.300.05 0.80 cc 1 2 3 0.65 0.05 0.85 0.05 0.01 + 0.04 - 0.01 (0.20) see detail a 5 0.08 c 0.10 c // 12 max c seating plane 16x (0.60) for the most recent package outline drawing, see l16.5x5d .

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